DESIGN AND OPTIMIZATION OF PATCH ANTENNA FOR WLL-COR-DECT TECHNOLOGY USING IE3D

SHAILESH MISHRA¹*, SATISH AWASTHI²*
¹Department of Electronics & Communication Engg., IIT Ghaziabad
²Department of Electronics & Communication Engg., ABES Ghaziabad
* Corresponding Author : awasthi_sateesh@rediffmail.com

Received : -     Accepted : -     Published : 21-12-2010
Volume : 1     Issue : 2       Pages : 1 - 4
Inform Sci Tech 1.2 (2010):1-4

Keywords : WLL-Cor-DECT, microstripline Patch antenna, Single feed, Input impedance, return loss, smith chart, optimization
Conflict of Interest : None declared
Acknowledgements/Funding : The authors would like to thank authorities of Ideal The authors would like to thank authorities of Ideal Institute of Technology for all the support provided

In this paper, we present a patch antenna for WLL- Cor-DECT Technology with resonance frequency of 1.88 GHz. The dielectric material selected for my design is Silicon which has a dielectric constant of 11.9. A substrate with a high dielectric constant has been selected since it reduces the dimensions of the antenna. For the microstrip patch antenna to be used in WLL System, it is essential that the antenna is not bulky. Hence, the height of the dielectric substrate is selected as 31 mil patch along with a single feed. The input impedance and return loss of the patch antenna are 388W and 5.8 dB, respectively. From the optimized results obtained, we get the return loss of below 35 dB at resonant frequency.

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